In order to make the cost of manufacturing an integrated circuit as small as possible, many instances of the integrated circuit are fabricated at one time onto a semiconductor wafer. After fabrication, each instance of the integrated circuit is separated from the wafer by sawing the wafer along the boundaries, or scribe lines, between each instance of the integrated circuit. An individual integrated circuit removed from a wafer is commonly referred to as a die. Each die may then be packaged and sold in a standard integrated circuit package (e.g., forty-pin leadless chip carrier) or not packaged at all and sold in die form. A purchaser of an integrated circuit in die form may then package the die in a non-standard package (e.g., a credit-card type package commonly referred to as a smart-card). Also, a purchaser of an integrated circuit in die form may place the die in a package along with another integrated circuit die. A package containing more than one die is commonly referred to as a multi-chip-module (MCM).
Non-standard packages containing a die and multi-chip-modules containing more than one die are becoming very popular because of there compactness and processing power. Manufacturers of such packages are always looking for ways to reduce the size or thickness of such packages. One way of reducing the thickness of such packages is to use die that are as thin as possible.
The minimum thickness required to realize a functional integrated circuit is around five microns. Typically, each integrated circuit fabricated on a wafer is around seven-hundred microns thick. Wafer die are this thick for manufacturing reasons and not for functional reasons. That is, to reduce the cost of an individual integrated circuit, many instances of the integrated circuit are fabricated at once on to a wafer. Wafers are ever increasing in size. The typical wafer today is around eight inches in diameter. In order to handle a wafer of this size without breaking it, the wafer has to be around seven-hundred microns thick.
Many methods exist for thinning a wafer but few methods exist for thinning individual die. U.S. Pat. No. 5,256,599, entitled "SEMICONDUCTOR WAFER WAX MOUNTING AND THINNING PROCESS," discloses a method of thinning an entire wafer. The wafer containing all of the dice fabricated therein is then used in its entirety. The present invention is not a method of thinning a wafer purchased in wafer form from a single manufacturer but a method of thinning individual die that are purchased in die form from any number of die manufacturers. Also, the present invention does not require the use of all of the die thinned by the present invention as a single device as does U.S. Pat. No. 5,256,599. U.S. Pat. No. 5,256,599 is hereby incorporated by reference into the specification of the present invention.
The ability to thin die has benefits over the ability to thin a wafer. Presently, a thinned wafer is used in its entirety. That is, all of the integrated circuits on the wafer are connected as one giant circuit and is packaged as such after it is thinned. The cost of an entire wafer is roughly equivalent to the cost of an individual die times the number of dice on the wafer. If a packager could thin a die then the packager would not be required to purchase thinned wafers and use them in their entirety. Therefore, costs are greatly reduced if individual die could be thinned. Also, a wafer that contains all of the die that a packager wishes to use may be custom to the packager. Custom circuits are, typically, much more expensive than commercially available circuits because custom circuits cannot be manufactured in as great a quantity as can commercially available circuits. Therefore, the ability to thin die would enable a packager to purchase state of the art die at commercial prices, select only those circuits that are required, thin them, and package only those thinned dice that are required.
U.S. Pat. No. 5,273,940, entitled "MULTIPLE CHIP PACKAGE WITH THINNED SEMICONDUCTOR CHIPS," discloses a method of electrically connecting standard thickness dice in a multi-chip-module, encapsulating the dice, and thinning the encapsulant and the dice. In this method, the dice are required to be electrically connected as a multi-chip-module prior to dice thinning. The manufacturing yield of the multi-chip-module can be no better than the dice thinning yield. Many good die would go to waste using this method because one bad die ruins the entire multi-chip-module. Presently, there is no way to do repairs at the multi-chip-module level. It is more cost effective to detect and correct a problem at the earliest point in the manufacturing process. The present invention is a method of thinning dice and testing them prior to electrically connecting them into a multi-chip-module. Therefore, the multi-chip-module yield is, theoretically, one-hundred percent using the present invention. U.S. Pat. No. 5,273,940 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,324,687, entitled "METHOD FOR THINNING OF INTEGRATED CIRCUIT CHIPS FOR LIGHTWEIGHT PACKAGED ELECTRONIC SYSTEMS," discloses a method of placing standard thickness dice circuit-side up in various wells in a semiconductor wafer. Each well has to be custom formed to accommodate the die placed therein. An adhesive layer in then placed over the face of each die. The adhesive is then bonded to a holding device. The semiconductor and, therefore, the dice are thinned from the backside of the dice to a desired thickness. The thinned dice and parts of the semiconductor wafer remaining between the dice may then be removed from the holding device and used in a multi-chip-module. In this method the semiconductor wafer must be customized to accept a certain set of dice. That is, the well sizes are determined by the dice used. If the size or thickness of the dice used changes then new wells must be formed into the wafer used to hold the dice to be thinned. Such customization is much more expensive as compared to a method that may be used for dice of any size or thickness such as the method of the present invention. U.S. Pat. No. 5,324,687 is hereby incorporated by reference into the specification of the present invention.